Analysis and mitigation of SEUs in ARM-based SoC on Xilinx Virtex-V SRAM-based FPGAs

Technology scaling enables the Field Programmable Gate Arrays (FPGAs) provide increasing computing power while remain low power consumption. Together with the high flexibility for application design and deployment, FPGAs have become popular even in safety- and mission-critical applications. Meanwhile, Commercial Off-The-Shelf (COTS) components are often used in system design to reduce time-to-market and development cost. In this paper, we are proposing a new method for the analysis and mitigation of Single Event Upsets (SEUs) on SRAM-based FPGAs. The method is based on an analytical analyzer algorithm able to accurately estimate the application error rate; furthermore, the same developed algorithm is able to implement mitigation rules. We present the radiation experiment results for analysis and mitigation of Single Event Upsets (SEUs) in an ARM-based SoC implemented on Xilinx Virtex-V FPGA demonstrating the feasibility of the analysis tool and the effectiveness of the mitigation method.