Chip Design of a Wave-Pipelined PRNG

Author

Sato, Tomoaki ; Kikuchi, Kazuhira ; Fukase, Masa-aki

Author_Institution

Comput. & Network Syst. Center, Hirosaki Univ.

fYear

2006

fDate

Oct. 18 2006-Sept. 20 2006

Firstpage

978

Lastpage

983

Abstract

Wave-pipelining technique has been one of most effective solutions for achieving speed and power conscious logic circuits. This attractive technique has been so far used in developing combinational circuits like adder, multiplier. In order to totally enhance the design activity of logic circuits, we have exploited the wave-pipelining of sequential circuits. Firstly we describe in this paper the wave-pipelining of LFSR (linear feedback shift register). Then, this has been evaluated by using CPLD (complex programmable logic device). From practical viewpoint, LFSR has played important roles as PRNG (pseudo-random number generator) within processors. Thus, we have finally designed the wave-pipelined PRNG by using 1.2-mum CMOS technology. The chip implementation of the waved-PRNG is very promising for highly performable and low-power processor chips

Keywords

CMOS logic circuits; integrated circuit design; pipeline arithmetic; programmable logic devices; random number generation; sequential circuits; shift registers; adders; chip design; complex programmable logic device; linear feedback shift register; low-power processor chips; multipliers; power conscious logic circuits; pseudorandom number generator; wave-pipelining technique; CMOS technology; Chip scale packaging; Clocks; Electronic mail; Logic circuits; Mobile computing; Personal digital assistants; Pipelines; Registers; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications and Information Technologies, 2006. ISCIT '06. International Symposium on

Conference_Location

Bangkok

Print_ISBN

0-7803-9741-X

Electronic_ISBN

0-7803-9741-X

Type

conf

DOI

10.1109/ISCIT.2006.339923

Filename

4141362