A forced-voltage technique to test data retention faults in CMOS SRAM by IDDQ testing

A novel technique to test data retention faults in a static CMOS memory cell is proposed. The proposed technique creates intermediate voltages in the faulty memory cell during the memorizing phase. In consequence, the quiescent current consumption (I_DDQ) increases and the fault can be detected sensing the I_DDQ. Testability regions for the memory cell are determined using state diagrams. A method is described to obtain the optimum testing conditions to test the data retention faults. A design for testability circuitry (DFT) required to implement the technique is proposed