A Novel Symbol Interleaver Address Generation Architecture for DVB-T Modulator

A new algorithm along with its hardware scheme has been proposed for consecutive generation of the symbol addresses involved in the symbol interleaving process of a digital video broadcast terrestrial (DVB-T) standard modulator. Advantages achieved through the utilization of this architecture in a DVB-T modulator design outperforms the one presented in the DVB-T standard. Using this technique the large buffer memory preceding the symbol interleaving block is avoided. In addition no further increase in the input bit rate of the modulator is needed. The design has also been implemented in FPGA. For further verification the design was also embedded in a real DVB-T modulator