Floating point adder/subtractor units realization by efficient arithmetic circuits

Floating point adder/subtractor units like fused floating point adder, triple path floating point adder, etc., involve exponent comparison/subtraction, mantissa addition/subtraction and incrementing values while rounding as basic operations. To realize these operations, efficient arithmetic units like comparators, adders, subtractors, and incrementers are vital. In this paper an efficient design of an adder and a design methodology for 2´s complement block is proposed which helps in design of floating point units.