Area-time tradeoffs in FIR digital filters with broadcast and pipelined designs

Previous designs of programmable finite impulse response (FIR) digital filters have demonstrated that the use of broadcast input data and control can lead to a high performance cost ratio. As we move towards widespread utilization of submicron technologies, such an approach should be reexamined by taking the effect of interconnections into account. In this paper, we show that the contribution of interconnect delay to the cycle time is no longer negligible and will hamper the scalability of the broadcast design. As an alternative, we propose a fully pipelined design in which both data and control signals are restricted to local connections. One important feature of our design is that the data input port can be reused to deliver the coefficients. Hence, the coefficients can be loaded in bit-parallel form with no increase in the number of input pins