Title :
A 1.0 μm CMOS all-digital clock multiplier
Author :
Cheng, Frankie King-Sun ; Cheong-Fat Chen ; Choy, Oliver Chiu-Sing
Author_Institution :
Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong
Abstract :
A simple all-digital clock multiplier base on a digital-controlled oscillator technique. The locking sequence is separated into two stages, frequency and phase locking, to reduce the number of locking cycles. This all-digital clock multiplier can generate a clock with a frequency range from 21 MHz to 39 MHz
Keywords :
CMOS logic circuits; clocks; multiplying circuits; phase locked oscillators; voltage-controlled oscillators; 1.0 micron; 21 to 39 MHz; CMOS all-digital clock multiplier; digital-controlled oscillator technique; frequency locking; locking cycles; locking sequence; phase locking; Clocks; Counting circuits; Digital control; Filters; Phase frequency detector; Phase locked loops; Pulse generation; Ring oscillators; Signal generators; Voltage-controlled oscillators;
Conference_Titel :
Circuits and Systems, 1997. Proceedings of the 40th Midwest Symposium on
Conference_Location :
Sacramento, CA
Print_ISBN :
0-7803-3694-1
DOI :
10.1109/MWSCAS.1997.666133
