Analysis of the source/drain parasitic resistance and capacitance depending on geometry of FinFET

The FinFET technology is one of the ultimate solutions for Moores Law. Since sizes of device channel shrink, several Short Channel Effects (SCEs) appear. The FinFET or Multigate are best solutions for SCEs. However, this device provides several parasitic components which may reduce the performance. The parasitic components are in form of parasitic resistance and in parasitic capacitance. Here, in this paper, source/drain region parasitic components with respect to geometry of FinFET are analyzed. The study shows S/D parasitic components are mainly dependent on the structural geometry of FinFET. The parasitic components w.r.t fin geometry as well as metal contact thickness have been analyze. So in order to reduce these parasitic the device geometry is to be optimized.