Abstract :
Non-binary low-density parity-check (NB-LDPC) codes over GF(q) (q > 2) have better error-correcting performance than their binary counterparts when the codeword length is moderate. In this paper, a modified trellis-based Min-max decoder is proposed for NB-LDPC codes. By relaxing the constraints on which messages can be included, the trellis syndrome computation is simplified without sacrificing the error-correcting performance. In addition, the iterative comparisons needed in computing the check-to-variable messages are replaced by one-step message selection. The decoding complexity of NB-LDPC codes grows substantially with q, and small q is preferred to achieve low complexity and high speed for data storage systems. Making use of the properties of G F (4), the hardware units are further simplified and efficient decoder architectures are developed for codes over G F (4). Compared to prior efforts, the proposed design requires smaller area, consumes much less power, achieves higher throughput, and also has slightly better error-correcting performance.
Keywords :
electronic messaging; error correction codes; iterative decoding; minimax techniques; parity check codes; trellis codes; NB-LDPC code decoding complexity; check-to-variable messages; codeword length; data storage system; error correcting performance; hardware unit; iterative comparisons; modified trellis-based minmax decoder; nonbinary low density parity check codes; one-step message selection; power consumption; trellis syndrome computation; Clocks; Complexity theory; Computer architecture; Decoding; Iterative decoding; Vectors; Low-density parity-check (LDPC) codes; Min-max algorithm; Non-binary; VLSI design;
