Title :
Design Margin Methodology for DDR Interface
Author :
Sarkar, Soujanna ; Brahme, Amit ; Chandar, Subash G.
Author_Institution :
Texas Instrum. (I) Pvt. Ltd., Bangalore
Abstract :
In this paper, we describe the design margin methodology that comprehends uncertainties at both chip and board level for a DDR-1 interface. These include effects that are not modeled in static timing analysis and SPICE. This methodology enables to predictably ensure silicon performance.
Keywords :
SPICE; logic design; system buses; timing; DDR interface; DDR-1 interface; SPICE; design margin methodology; static timing analysis; Computational modeling; Delay; Design methodology; Digital control; Impedance; Manufacturing; SPICE; Silicon; Timing; Uncertainty;
Conference_Titel :
Electrical Performance of Electronic Packaging, 2007 IEEE
Conference_Location :
Atlanta, GA
Print_ISBN :
978-1-4244-0883-2
DOI :
10.1109/EPEP.2007.4387151
