Title :
A reconfigurable data-flow architecture for a class of image processing applications
Author :
Sinha, A. ; Neogi, S. ; Maiti, K.
Author_Institution :
R&D Center, Himachal Futuristic Commun. Ltd., Gurgaon, India
Abstract :
This paper aims to device an architecture which uses the capability of asynchronous concurrency of the data flow architecture as well as spatial parallelism of SIMD machines for a class of image processing applications using reconfigurable processing elements (RPE). Overall processing speed is enhanced by: (a) concurrent functioning of the RPE; and (b) replacing software execution of signal processing functions by hardware approach using FPGA as RPE. Thus, a hybrid architecture, which functions as a data flow machine at a functional level and exploits the capability of spatial parallelism by incorporating modified SIMD concepts is presented.
Keywords :
data flow computing; field programmable gate arrays; image processing; parallel architectures; reconfigurable architectures; FPGA; SIMD machines; asynchronous concurrency; concurrent functioning; hardware approach; hybrid architecture; image processing applications; processing speed; reconfigurable data-flow architecture; spatial parallelism; Application software; Computer architecture; Concurrent computing; Data flow computing; Field programmable gate arrays; Hardware; Image processing; Parallel processing; Signal processing; Signal processing algorithms;
Conference_Titel :
Circuits and Systems for Communications, 2002. Proceedings. ICCSC '02. 1st IEEE International Conference on
Print_ISBN :
5-7422-0260-1
DOI :
10.1109/OCCSC.2002.1029140
