SMDAC design with nested gain boosted opamp for a 14-bit 200-MS/s pipelined ADC

This paper presents a design of merged active SHA (sample and hold amp) and first MDAC (SMDAC) used in the first 4-bit pipeline stage of an analog-to-digital converter (ADC). A nested gain boosting technique is first used on the signal path to obtain the required resolution without increasing too much power. A constant-transconductance (constant-gm) bias circuit is designed for corner robustness and a bootstrapped switch is also employed. The circuit is designed in 0.13-μm CMOS with 120mW power consumption under 1.5 V supply voltage, and the simulation results show that the designed SMDAC is suitable for 14-bit 200-MS/s pipelined ADC.