A novel graphics processor architecture based on partial stream rewriting

Although individual stages of current graphics processing units (GPU) are programmable via shaders, the pipeline still contains fixed blocks and the data flow cannot be adjusted arbitrary. To overcome these limitations, we propose a novel graphics processor architecture, which substantially improves reconfigurability of the rendering pipeline. For this purpose, we model the complete rendering pipeline as a functional program, which is then represented as a stream of tokens and iteratively modified by a set of rewriting rules. Our proposed architecture enables dynamic thread creation, lock-free synchronization and light-weight scheduling based on pattern matching. Reconfigurability and scalability of the novel processor architecture are demonstrated by complex examples running on an FPGA prototype.