The gate misalignment effects of the sub-threshold characteristics of sub-100 nm DG-MOSFETs

In this paper, simulation results of the gate misalignment effects on the sub-threshold characteristics of asymmetric (ADG) and symmetric (SDG) double-gate MOSFET (DG-MOSFET) in the sub-100 nm regime are presented. Gates alignment in DG-MOSFETs becomes more and more difficult as devices are scaling down in non-self-aligned double-gate processes. The results show that gate misalignment effects are not as serious as generally expected and 60-80% misalignment is considered to be tolerable in some circuit applications.