Title :
The gate misalignment effects of the sub-threshold characteristics of sub-100 nm DG-MOSFETs
Author :
Wong, Hiu Yung ; Shin, Kyoungsub ; Chan, Mansun
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
Abstract :
In this paper, simulation results of the gate misalignment effects on the sub-threshold characteristics of asymmetric (ADG) and symmetric (SDG) double-gate MOSFET (DG-MOSFET) in the sub-100 nm regime are presented. Gates alignment in DG-MOSFETs becomes more and more difficult as devices are scaling down in non-self-aligned double-gate processes. The results show that gate misalignment effects are not as serious as generally expected and 60-80% misalignment is considered to be tolerable in some circuit applications.
Keywords :
MOSFET; 100 nm; asymmetric double-gate MOSFET; gate misalignment; nonself-aligned double-gate process; subthreshold characteristics; symmetric double-gate MOSFET; Computational modeling; Computer simulation; Costs; Dielectric constant; Fabrication; Inorganic materials; MOSFET circuits; Medical simulation; Protection; Threshold voltage;
Conference_Titel :
Electron Devices Meeting, 2002. Proceedings. 2002 IEEE Hong Kong
Print_ISBN :
0-7803-7429-0
DOI :
10.1109/HKEDM.2002.1029164
