A hierarchical Ant-Colony heuristic for architecture synthesis for on-chip communication

Architecture synthesis and high level synthesis are the paradigms to efficiently organize computations and communications at the high level. While research has been extensively conducted to solve those two problems, a gap between those two paradigms still exists. This paper presents an algorithm for architectural tradeoff for on-chip communication at operation-level granularity. Applied to practical Digital Signal Processing (DSP) and image processing applications, the algorithm can generate superior results over the state-of-the-art ones, while running in sub-quadratic time. Due to the low run time complexity, the algorithm is able to provide task-level applications with solutions that completely describe when and where operations and operands are executed and transferred, respectively. In practice, this opens an opportunity to substantially narrow the gap between high level and architecture level synthesis.