State diagram design for implementing phase I of a Vector Symbol Decoder on an FPGA board

The principle of vector symbol decoding (VSD) has been shown as a powerful decoding technique. This paper focused on the implementation of the phase I of convolutional VSD decoder that can correct some error pattern using only one syndrome. Specifically, it is on how to design the state diagram for the interface of the test system and the state diagram for the decoding algorithm. The state design was for the VHDL programming and the implementation on an FPGA board. The test results showed that the phase I VSD decoder worked as designed