A High-Performance Memory-Efficient Parallel Hardware for Matrix Computation in Signal Processing Applications

This paper introduces a new versatile and high-performance parallel hardware engine for matrix computations. The proposed architecture reduces memory bandwidth by taking advantage of data redundancies and employing distributed memory structures. It is designed to better utilize the on chip area for computing different types of matrix computations such as matrix power, multiplication, and inversion. The matrix power presented in this paper is proven to be two times faster than normal computations. As well, the architecture is optimized to suitably perform least square computations in signal processing applications. The synthesis results on FPGA platforms indicate that the proposed architecture can operate in 75 MHz for 16 bit word length and the peak attained performance is about 2400 MMAC operations with 32 concurrent MAC modules