VLSI Implementation of High-Throughput SISO-OFDM and MIMO-OFDM Transceivers

This report describes the implementation of high-throughput OFDM transceivers targeted to future wireless LAN systems. The optimum parameters constructing a new packet OFDM frame are considered by expanding the IEEE 802.11a standard. The proposed system provides a maximum of 600 Mbps by use of an 80-MHz baseband bandwidth and a 2times2 MIMO scheme. The SISO-OFDM and MIMO-OFDM transceivers have been designed according to the proposed OFDM parameters. A low-latency and full-pipelined architecture enables the real-time operations of OFDM modulation and MIMO detection. In a 90-nm CMOS technology, the SISO-OFDM and MIMO-OFDM transceivers have 1.4 and 3.1 millions in logic gates and consume 259 and 535 mW in power dissipation, respectively. The FPGA board has been developed to verify their circuit behavior, which is connected to RF and antenna modules