DocumentCode :
2180918
Title :
VLSI Implementation of High-Throughput SISO-OFDM and MIMO-OFDM Transceivers
Author :
Yoshizawa, Shingo ; Miyanaga, Yoshikazu
Author_Institution :
Graduate Sch. of Inf. Sci. & Technol., Hokkaido Univ., Sapporo
fYear :
2006
fDate :
Oct. 18 2006-Sept. 20 2006
Firstpage :
483
Lastpage :
486
Abstract :
This report describes the implementation of high-throughput OFDM transceivers targeted to future wireless LAN systems. The optimum parameters constructing a new packet OFDM frame are considered by expanding the IEEE 802.11a standard. The proposed system provides a maximum of 600 Mbps by use of an 80-MHz baseband bandwidth and a 2times2 MIMO scheme. The SISO-OFDM and MIMO-OFDM transceivers have been designed according to the proposed OFDM parameters. A low-latency and full-pipelined architecture enables the real-time operations of OFDM modulation and MIMO detection. In a 90-nm CMOS technology, the SISO-OFDM and MIMO-OFDM transceivers have 1.4 and 3.1 millions in logic gates and consume 259 and 535 mW in power dissipation, respectively. The FPGA board has been developed to verify their circuit behavior, which is connected to RF and antenna modules
Keywords :
CMOS integrated circuits; MIMO communication; OFDM modulation; VLSI; field programmable gate arrays; radiofrequency integrated circuits; transceivers; wireless LAN; 600 Mbit/s; 80 MHz; CMOS technology; FPGA board; IEEE 802.11a standard; MIMO-OFDM transceivers; VLSI implementation; full-pipelined architecture; high-throughput SISO-OFDM; wireless LAN systems; Bandwidth; Baseband; CMOS logic circuits; CMOS technology; Logic gates; MIMO; OFDM modulation; Transceivers; Very large scale integration; Wireless LAN;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications and Information Technologies, 2006. ISCIT '06. International Symposium on
Conference_Location :
Bangkok
Print_ISBN :
0-7803-9741-X
Electronic_ISBN :
0-7803-9741-X
Type :
conf
DOI :
10.1109/ISCIT.2006.339993
Filename :
4141432
Link To Document :
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