DocumentCode :
2181073
Title :
An efficient GPU implementation of an arbitrary resampling polyphase channelizer
Author :
Kim, Scott C. ; Plishker, William L. ; Bhattacharyya, Shuvra S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Maryland at, College Park, MD, USA
fYear :
2013
fDate :
8-10 Oct. 2013
Firstpage :
231
Lastpage :
238
Abstract :
A channelizer is a part of a receiver front-end subsystem, commonly found in various communication systems, that separates different users or channels. A modern channelizer uses advantages of polyphase filter banks to process multiple channels at the same time, allowing down conversion, downsampling, and filtering all at the same time. However, due to limitations imposed by the structure and requirements of channelizers, their usage is limited and poses significant challenges due to inflexibility using conventional implementation techniques, which are intensively hardware-based. However, with advances in graphics processing unit (GPU) technology, we now have the potential to deliver high computational throughput along with the flexibility of software-based implementation. In this paper, we demonstrate how this potential can be exploited by presenting a novel GPU-based channelizer implementation. Our implementation incorporates methods for eliminating complex buffer managements and performing arbitrary resampling on all channels simultaneously. We also introduce the notion of simultaneously processing many channels as a high data rate parallel receiver system using blocks of threads in the GPU. The multi-channel, flexible, high-throughput, and arbitrary resampling characteristics of our GPU-based channelizer make it attractive for a variety of communication receiver applications.
Keywords :
graphics processing units; radio receivers; GPU implementation; arbitrary resampling; arbitrary resampling polyphase channelizer; buffer management; communication receiver applications; communication systems; computational throughput; down conversion; downsampling; filtering; graphics processing unit; high data rate parallel receiver system; polyphase filter banks; receiver front-end subsystem; software-based implementation; Discrete Fourier transforms; Graphics processing units; Hardware; IP networks; Instruction sets; Interpolation; Receivers; DSP accelerator; arbitrary resampling; front-end receiver; polyphase channelizer; sample rate conversion;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design and Architectures for Signal and Image Processing (DASIP), 2013 Conference on
Conference_Location :
Cagliari
Type :
conf
Filename :
6661548
Link To Document :
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