Over-Sampling PLL for Low-Jitter and Responsive Clock Synchronization

phase locked loops (PLLs) are widely used in communication and required to provide low-jitter and fast frequency/phase locking capabilities. For improving these capabilities of PLL, an over-sampling phase detector (PD) using phase interpolation based on a counter with a high-frequency internal clock is proposed. PLL using normal PD compares phases of reference or input signal with its output at the time of their positive transition, but this PLL using over-sampling PD can compare phases more than once a cycle of reference. Thus, the PLL features less jitter than PLL using normal PD, and improved responsiveness. Also we optimized implementation of phase interpolation, to improve maximum operating frequency and circuit size. Experimental results including two jitter characteristics, vital in communication, are shown