Title :
An All-Digital Delay-Locked Loop Using a New LPF State Machine
Author :
Wang, Zhijun ; Liang, Liping ; Wang, Xingjun
Author_Institution :
Res. Inst. of Inf. Technol., Tsinghua Univ., Beijing
fDate :
Oct. 18 2006-Sept. 20 2006
Abstract :
An all-digital delay-locked loop (DLL) is presented in this paper. A new variable-step LPF state machine and a variable taps delay line are used here to achieve shorter lock in time than classical digital DLLs. The design is implemented in 0.18 mum CMOS technology. The experiment results show that the all-digital DLL can run at the frequency of about 800 MHz. The power dissipation of the DLL core is about 110 mW under a 1.8 V power supply
Keywords :
CMOS digital integrated circuits; delay lock loops; finite state machines; CMOS technology; LPF state machine; all-digital delay-locked loop; power dissipation; variable taps delay line; CMOS technology; Circuit noise; Circuit stability; Circuit testing; Clocks; Convergence; Delay effects; Delay lines; Shift registers; Signal generators;
Conference_Titel :
Communications and Information Technologies, 2006. ISCIT '06. International Symposium on
Conference_Location :
Bangkok
Print_ISBN :
0-7803-9741-X
Electronic_ISBN :
0-7803-9741-X
DOI :
10.1109/ISCIT.2006.339843
