A completely integrated single-chip PLL with a 34 GHz VCO using 0.2 μm E-/D-HEMT-technology

Author

Lang, M. ; Leber, P. ; Wang, Z.G. ; Lao, Z. ; Rieger-Motzer, M. ; Bronner, W. ; Hülsmann, A. ; Kaufel, G. ; Raynor, B.

Author_Institution

Fraunhofer-Inst. of Appl. Solid-State Phys., Freiburg, Germany

fYear

1997

fDate

5-8 May 1997

Firstpage

529

Lastpage

532

Abstract

A completely integrated single-chip phase locked loop based on a 0.2 μm gate length enhancement/depletion AlGaAs-GaAs-AlGaAs-HEMT technology has been designed and characterized. The chip contains a VCO with 34 GHz center frequency, a dynamic frequency divider by two, a static divider by eight, a phase detector, and a loop filter. The chip size is 2.0×1.5 mm². The power consumption is 1.2 W at a supply voltage of -5.0 V. The locking range is approximately ±700 MHz. The phase noise of locked PLL is -83 dBc/Hz at 100 kHz and -102 dBc/Hz at 1 MHz offset from the carrier frequency, respectively

Keywords

HEMT integrated circuits; III-V semiconductors; aluminium compounds; field effect MIMIC; gallium arsenide; millimetre wave oscillators; phase locked loops; phase noise; voltage-controlled oscillators; -5 V; 0.2 micron; 1.2 W; 34 GHz; AlGaAs-GaAs-AlGaAs; E-/D-HEMT-technology; EHF; MM-wave VCO; depletion HEMT; dynamic frequency divider; enhancement HEMT; loop filter; phase detector; phase locked loop; phase noise; single-chip PLL; static divider; Circuits; Filters; Frequency conversion; Impedance; Phase detection; Phase frequency detector; Phase locked loops; Signal generators; Virtual colonoscopy; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606682

Filename

606682