Nonlinear thermo-mechanical analysis of TSV interposer filling with solder, Cu and Cu-cored solder

The coefficient of thermal expansion (CTE) of metal (e.g., copper, tungsten and solder) filled in through silicon via (TSV) is a few times higher than that of silicon. Thus, when the metal filled TSV is subjected to temperature loadings, there is a very large local thermal expansion mismatch between the metal and the silicon/dielectric (e.g., SiO2), which will create very large stresses at the interfaces between the metal and the silicon and between the metal and the dielectric. These stresses can be high enough to introduce delamination between the interfaces. In this paper, we present a Cu-cored solder via filling method to form a low-resistance via interconnect. The initial results with the Cu-cored solder via filling are reported. This method offers a rapid, low-cost process for TSV manufacturing. The thermo-mechanical analysis of TSV interposer via filling with solder, Cu and Cu-cored solder were studied to understand the reliability issues in using different filling materials. The nonlinear thermal stresses at the interfaces between the copper, solder, silicon, and dielectric have been determined for a wide-range of aspect ratios (of the interposer height and the TSV diameter).