Elimination of nonlinear clock feedthrough in component-simulation switched-current circuits

This paper discusses a technique for the cancellation of clock feedthrough effects in component-simulation switched-current filters, based on a scaled replication of the parts of the circuit that control the filter coefficients. The regular structure of these filters is particularly convenient for the application of the technique, that can also be applied to other structures. As an additional benefit, considerable layout simplification can be obtained, because the same technique cancels systematic errors in transistor widths, allowing layouts to be done without splitting the coefficient-controlling transistors in several identical units, as is usually done for better matching