A high performance, high density sea of modules FPGA architecture

Author

El-Ayat, K. ; Kaptanoglu, S. ; Chan, R. ; Lien, J. ; Plants, W. ; Asayesh, R. ; Cheng, L. ; Lambertson, R. ; Bakker, G. ; El-Toukhy, A. ; Chew, M. ; Gopissety, R. ; Miller, W. ; Ku, S.

Author_Institution

Actel Corp., Sunnyvale, CA, USA

fYear

1997

fDate

5-8 May 1997

Firstpage

535

Lastpage

538

Abstract

Functionality and flexibility has been significantly enhanced with this novel sea of modules FPGA architecture. It includes a new improved logic cell, high performance interconnect architecture and full featured fracturable flip flops. The architecture is designed for high in system performance as well as low cost user programmable implementations. A flexible high performance I/O architecture complements the architecture with high performance input/output delays. A modular architecture and design methodology allows quick proliferation to multiple families while tailoring the individual family characteristics to quickly serve a particular market segment. The family uses a novel metal to metal antifuse technology that affords high performance, scalability and cost reduction

Keywords

field programmable gate arrays; flip-flops; integrated circuit interconnections; logic design; FPGA architecture; cost reduction; design methodology; flexible I/O architecture; fracturable flip flops; high density sea of modules; high performance interconnect architecture; input/output delays; logic cell; metal to metal antifuse technology; modular architecture; scalability; Costs; Design methodology; Field programmable gate arrays; Fuses; Integrated circuit interconnections; Investments; Logic circuits; Logic functions; Scalability; Space technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606683

Filename

606683