Title :
An improved partitioning method using clustering refinement [VLSI design]
Author :
Kim, Namhoon ; Kim, Chunghee ; Shin, Hyunchul
Author_Institution :
Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea
Abstract :
Partitioning is an important step in the hierarchical design of very large scale integrated circuits. In this research, an improved partitioning based on 2-level hierarchy has been developed. New techniques for clustering and cluster refining have been developed. After clusters are formed, they can be refined by moving cells among the clusters. For partitioning, the hierarchical gradual constraint enforcing partitioning method has been used. The clustering-based partitioning algorithm has been applied to MCNC benchmark examples and produced excellent results
Keywords :
VLSI; circuit CAD; integrated circuit design; iterative methods; 2-level hierarchy; HGCEP algorithm; VLSI circuits; clustering refinement; clustering-based partitioning algorithm; hierarchical design; hierarchical gradual constraint enforcing method; partitioning method; very large scale integrated circuits; Annealing; Circuits; Clustering algorithms; Design engineering; Iterative algorithms; Iterative methods; Large-scale systems; Partitioning algorithms; Pins; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-3702-6
DOI :
10.1109/APCAS.1996.569276
