A 3.3-V programmable logic device that addresses low power supply and interface trends

Author

Patel, Rakesh ; Wong, Wilson ; Lam, John ; Lai, Tin ; White, Tom ; Cheung, Sammy

Author_Institution

Altera Corp., San Jose, CA, USA

fYear

1997

fDate

5-8 May 1997

Firstpage

539

Lastpage

542

Abstract

This paper discusses a 3.3 V programmable logic device family which provides up to 130 Kgates. It blends a multi-dimensional interconnect scheme, logic array block approach consisting of 6,656 logic elements and circuit techniques to address low power supply and interface trends. It is designed on a 0.35 μm triple metal-dual oxide process to operate in a 3.3 V only, 5 V only or 3.3 V-5 V systems. Under worst case operating conditions it was observed to have a typical system operating frequency of 90 MHz. The EPF10K50V is the first member of the second-generation FLEX 10K family

Keywords

CMOS logic circuits; programmable logic arrays; 0.35 micron; 3.3 V; 5 V; 90 MHz; EPF10K50V; PLD family; logic array block; low power supply; multi-dimensional interconnect scheme; programmable logic device; second-generation FLEX 10K family; triple metal-dual oxide proces; Costs; Driver circuits; Flexible printed circuits; Logic arrays; Logic circuits; Logic devices; Power supplies; Programmable logic devices; Switches; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606684

Filename

606684