Title :
Moore´s Law Past 32nm: Future Challenges in Device Scaling
Author_Institution :
Logic Technol. Dev., Intel Corp., Hillsboro, OR
Abstract :
This paper explores the challenges facing process generations past the 32 nm technology node and speculates on what new solutions will be needed. The challenges facing planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, as well as NMOS and PMOS stress are discussed in relation to the challenges of the coming transistor generations.
Keywords :
MOSFET; high-k dielectric thin films; Moore´s Law; NMOS stress; PMOS stress; channel orientation; device scaling; high-k metal-gate; multiple-gate devices; planar devices; substrate orientation; Capacitance; Capacitive sensors; Degradation; Doping; Electrostatic discharge; History; MOS devices; Moore´s Law; Stress; Transistors;
Conference_Titel :
Computational Electronics, 2009. IWCE '09. 13th International Workshop on
Conference_Location :
Beijing
Print_ISBN :
978-1-4244-3925-6
Electronic_ISBN :
978-1-4244-3927-0
DOI :
10.1109/IWCE.2009.5091124
