DocumentCode
2183802
Title
A stage-reduced low-latency successive cancellation decoder for polar codes
Author
Liu, Xing ; Sha, Jin ; Zhang, Chuan ; Wang, Zhongfeng
Author_Institution
Nanjing University, China
fYear
2015
fDate
21-24 July 2015
Firstpage
258
Lastpage
262
Abstract
Polar codes, which are the first capacity achieving codes, have recently become increasingly popular because of their low encoding and decoding complexity. However, the large code length required by practical applications leads to high decoding latency because the conventional successive cancellation (SC) decoder decodes bits serially. This brief first reviews the conventional SC decoder briefly. An improved SC decoder architecture is given, which reduces the decoding latency by 25% compared to the conventional one. Then a stage-reduced SC decoding algorithm and its low-latency architecture is presented. Compared with the conventional SC decoder, the proposed stage-reduced SC decoder achieves almost 50% latency reduction with no performance degradation and acceptable hardware overhead. A kind of 2-stage-reduced SC decoding algorithm is also investigated in this brief.
Keywords
Approximation methods; Clocks; Computer architecture; Decoding; Degradation; Hardware; Schedules; decoder architecture; polar codes; stage-reduced; successive cancellation decoding;
fLanguage
English
Publisher
ieee
Conference_Titel
Digital Signal Processing (DSP), 2015 IEEE International Conference on
Conference_Location
Singapore, Singapore
Type
conf
DOI
10.1109/ICDSP.2015.7251871
Filename
7251871
Link To Document