A high-speed arbitration scheme for an input buffering ATM switch architecture

This paper proposes a high-speed arbitration scheme featuring high flexibility to bursty traffic for an input buffering ATM switch architecture and its hardware strategy. The arbitration sequence is given based on the threshold of the occupancy of the input buffer. The hardware strategy for the proposed policy is presented with the aim of simplifying the structure. The performance of the average buffer size of the proposed policy is performed and compared with the conventional scheme under bursty traffic conditions through simulation