Title :
Design of 1-kbit antifuse OTP memory IP using dual program voltage and its measurement
Author :
Jang, Ji-Hye ; Yang, Huiling ; Jin, Liyan ; Ha, Pan-Bong ; Kim, Young-Hee
Author_Institution :
Dept. of Electron. Eng., Changwon Nat´´l Univ., Changwon, South Korea
Abstract :
In this paper, we design a 1-kbit antifuse OTP (one time programmable) memory IP which is used for power management ICs. A conventional antifuse OTP cell using a single VPP (positive program voltage) has a problem about applying a higher voltage than the breakdown voltage to thin gate oxides and securing the reliability of MV (medium voltage) devices which are thick gate transistors at the same time. Thus, we design and measure a 1-kbit antifuse OTP breaking down hard the thin gate oxides by using dual program voltage: VPP (positive program voltage) and VNN (negative program voltage). It is designed with Dongbu HiTek´s 0.18 μm BCD (Bipolar-CNOS DMOS) process and its yield is 80% when three series of continuous programming are done on 56 test dies at the following program voltages : VPP=8V and VNN-2V.
Keywords :
BiCMOS integrated circuits; CMOS memory circuits; MOSFET; power integrated circuits; random-access storage; semiconductor device reliability; BCD process; MOS transistor; MV device; VNN; VPP; antifuse OTP memory IP; antifuse one time programmable memory IP; bipolar-CNOS-DMOS process; dual program voltage; medium voltage device; negative program voltage; positive program voltage; power management IC; size 0.18 mum; thick gate transistor; thin gate oxide; voltage -2 V; voltage 8 V; voltage breakdown; Decoding; Driver circuits; Latches; Logic gates; Nonvolatile memory; Switches; Transistors;
Conference_Titel :
Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), 2011 8th International Conference on
Conference_Location :
Khon Kaen
Print_ISBN :
978-1-4577-0425-3
DOI :
10.1109/ECTICON.2011.5947785
