• DocumentCode
    2184527
  • Title

    Test structure designed for vias in multi-layer package substrate

  • Author

    Ling, Sun ; Ling-ling, Yang ; Hai-yan, Sun ; Shenglong, Wang

  • Author_Institution
    Jiangsu Key Lab. of ASIC Design, Nantong Univ., Nantong, China
  • fYear
    2011
  • fDate
    8-11 Aug. 2011
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    A symmetrical test structure for the measurement of vias in multi-layer package substrate was put forward in this paper. Based on the known S-parameters of this designed symmetrical structure and the deduced expressions, an indirect method to get the actual S-parameters of a single via was presented. In order to verify the validity of the proposed method, the simulation models were built in Power SI environment from SIGRITY. After a comparison between the simulated and calculated results, the correctness of the proposed method was proved.
  • Keywords
    S-parameters; electronics packaging; multilayers; S parameters; SIGRITY; multi layer package substrate; symmetrical test structure; vias; Electronics packaging; Integrated circuit modeling; Mathematical model; Packaging; Periodic structures; Scattering parameters; Substrates;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Packaging Technology and High Density Packaging (ICEPT-HDP), 2011 12th International Conference on
  • Conference_Location
    Shanghai
  • Print_ISBN
    978-1-4577-1770-3
  • Electronic_ISBN
    978-1-4577-1768-0
  • Type

    conf

  • DOI
    10.1109/ICEPT.2011.6066873
  • Filename
    6066873