Accuracy analysis of layout parasitic extraction based on Boolean methods

Layout parasitic extraction methods based on Boolean operation of layers are well established in design practice. They are developed on hypotheses that the layout can be considered as a two dimensional structure and that net capacitances depend only on the net area and perimeter values. In the paper, we show with the aid of layout structures that these hypotheses are now not valid for submicron layout technology and thus relevant errors are introduced in the estimation of the net capacitances