Design and measurement of a small-area 512-Bit EEPROM

In this paper, a logic process based small-area 512-bit EEPROM IP for a passive RFID tag chip is designed. We propose a shared CG (Control gate) driver structure in the EEPROM core circuit for a small-area IP design. Devices of 3.3 V are limited within S.SV in the write mode to secure the endurance of 1,000 erase and program cycles as well as ten years of data retention. To meet the above conditions, we use a three-stage voltage level translator circuit in the CG driver. Also, we propose a DOUT buffer circuit to output a selected read datum by latching two words of BL (Bit line) data. The layout area of the designed 512-bit EEPROM IP with c-flash cells of Tower´s 0.18 μm process is 373.96μm × 434.04μm. It is confirmed by the computer simulation that the power dissipation is 0.35 μW in the read mode, 13.76 μW in the program mode, and 13.66 μW in the erase mode, respectively. It is also confirmed by the experiment that the test chip is functioning normally.