Fast rate distortion optimization design for HEVC intra coding

Various coding structures and modes in the latest High Efficiency Video Coding (HEVC) standard result in significant computation of rate distortion optimization to decide the best one. To fit the real time demand, this paper proposes a hardware-friendly Rate-Distortion Estimation algorithm and its hardware design. For bit rate estimation, we propose a linear model based on the histogram of quantized coefficients instead of serial arithmetic coding computation in the reference software for speedup. For the distortion estimation, we use the transform domain instead of spatial domain estimation to save inverse transform computation. The simulation results shows 3.49% BD-rate increase on average compared to reference software. The hardware implementation with TSMC 90nm CMOS costs 50K logic gates which can support the processing with 16 pixels per cycle at 270MHz operation frequency.