A field programmable gate array chip with hierarchical interconnection structure

Author

Lai, Yen-Tai ; Kao, Chi-Chou ; Chang, Tsun-Chen ; Chen, Kun-Nern

Author_Institution

Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan

Volume

2

fYear

1998

fDate

31 May-3 Jun 1998

Firstpage

402

Abstract

This paper presents the architecture and implementation of a field programmable gate array chip with hierarchical interconnection structure. The new field programmable gate array has higher performance than conventional field programmable gate arrays. Its advantages are high density, fast speed, and the flexibility to fit designs into the architecture quickly. The schematic circuit of the FPGA is described, and its layout by using full-custom top-down method is presented

Keywords

application specific integrated circuits; field programmable gate arrays; integrated circuit interconnections; integrated circuit layout; logic CAD; architecture; density; field programmable gate array chip; full-custom top-down method; hierarchical interconnection structure; layout; schematic circuit; speed; Application specific integrated circuits; Costs; Design methodology; Field programmable gate arrays; Integrated circuit interconnections; Logic arrays; Logic devices; Prototypes; Switches; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on

Conference_Location

Monterey, CA

Print_ISBN

0-7803-4455-3

Type

conf

DOI

10.1109/ISCAS.1998.706961

Filename

706961