DocumentCode
2185118
Title
An analog layout floorplanner using its parameterized module layout structure
Author
Kim, Young Soo ; Yoon, Kwang Sub
Author_Institution
Dept. of Electron. Eng., Inha Univ., Inchon, South Korea
fYear
1996
fDate
18-21 Nov 1996
Firstpage
397
Lastpage
400
Abstract
This paper presents an analog layout floorplanner whose module library is parameterized with its layout structure. The developed floorplanner employs the parameterized layout template that enhances the CIF (Caltech Intermediate Form) description language. By utilizing this template, the complexity of the generator text is reduced, and an additional complex parser and analyzer are not required. This floorplanner has been tested on several benchmark circuits and displayed six to ten times of generator text reduction
Keywords
analogue integrated circuits; circuit layout CAD; integrated circuit layout; CIF description language; analog layout floorplanner; complexity reduction; generator text reduction; parameterized module layout structure; Automation; Benchmark testing; Circuit testing; Computer languages; Cost function; Engines; Geometry; Humans; Libraries; Simulated annealing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location
Seoul
Print_ISBN
0-7803-3702-6
Type
conf
DOI
10.1109/APCAS.1996.569299
Filename
569299
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