An effective routing methodology for Gb/s LSI using deep submicron CMOS/SIMOX technology

Author

Watanabe, Takumi ; Ohtomo, Yusuke ; Yamakoshi, Kimihiro ; Takei, Yuichiro

Author_Institution

NTT Syst. Electron. Labs., Kanagawa, Japan

fYear

1997

fDate

5-8 May 1997

Firstpage

569

Lastpage

572

Abstract

This paper presents the routing methodology and CAD tools used in designing Gb/s LSIs with deep submicron technology. A routing method for controlling wire width and spacing is adopted for each net group classified by wire length and the permitted delay constraints. A high-performance router and a high-precision delay analyzer adapted to the methodology have been developed. The methodology has been applied in the design of an ATM-switch LSI using 0.25 μm CMOS/SIMOX technology. The LSI has a throughput of 40 Gb/s (2.5 Gbps/pin) and an internal clock frequency of 312 MHz

Keywords

CMOS digital integrated circuits; SIMOX; asynchronous transfer mode; circuit layout CAD; delays; field effect transistor switches; integrated circuit layout; large scale integration; network routing; 0.25 micron; 312 MHz; 40 Gbit/s; ATM-switch LSI; CAD tools; Gb/s LSI; IC design; deep submicron CMOS/SIMOX technology; delay constraints; high-performance router; high-precision delay analyzer; routing methodology; wire spacing; wire width; CMOS technology; Capacitance; Clocks; Delay effects; Design automation; Frequency; Large scale integration; Routing; Throughput; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997

Conference_Location

Santa Clara, CA

Print_ISBN

0-7803-3669-0

Type

conf

DOI

10.1109/CICC.1997.606691

Filename

606691