Title :
A 3-V, 1.47-mW, 120-MHz comparator for use in a pipeline ADC
Author :
Ho, Jeffrey ; Luong, Howard Cam
Author_Institution :
Dept. of Electr. & Electron. Eng., Hong Kong Univ. of Sci. & Technol., Kowloon, Hong Kong
Abstract :
A low-voltage and low-power comparator suitable for use in a pipeline analog-to-digital converter is implemented in CMOS 0.8 μm technology. The maximum clock frequency with DC inputs is 160 MHz. With a 10 MHz input sine wave at vi+, DC at vi-, and a clock frequency of 120 MHz, the measured rise-time, fail-time, delay-time, and power consumption are 1.28 ns, 1.37 ns, 1.60 ns and 1.47 mW, respectively. The optimization issue of the comparator is discussed
Keywords :
CMOS integrated circuits; analogue-digital conversion; circuit optimisation; pipeline processing; 0.8 micron; 1.28 to 1.6 ns; 1.47 mW; 120 MHz; 160 MHz; 3 V; CMOS comparator; analog-to-digital converter; low-power comparator; low-voltage comparator; pipeline ADC; Analog-digital conversion; CMOS technology; Clocks; Flip-flops; Frequency; Hardware; Pipelines; Propagation delay; Rails; Voltage;
Conference_Titel :
Circuits and Systems, 1996., IEEE Asia Pacific Conference on
Conference_Location :
Seoul
Print_ISBN :
0-7803-3702-6
DOI :
10.1109/APCAS.1996.569303
