FPGA implementation for stereo matching algorithm

To reach a real-time stereo vision in embedded systems, we propose in this paper, the adaptation and optimization of the well-known Disparity Space Image (DSI) on a single FPGA(Field programmable gate Arrays) that is designed for high efficiency when realized in hardware. An initial disparity map was calculated using the DSI structure and then a median filter was applied to smooth the disparity map. Many methods reported in the literature are mainly restricted to implement the SAD algorithm (Sum of Absolute Differences) on an FPGA. An evaluation of our method is done by comparing the obtained results of our method with a very fast and well-known sum of absolute differences algorithm using hardware-based implementations.