Title :
ISA Based Functional Test Generation with Application to Self-Test of RISC Processors
Author :
Belkin, V.V. ; Sharshunov, S.G.
Abstract :
This paper presents a method for functional test generation, which aims self-test of RISC processors and processor cores. The method allows developing compact and quite effective software based tests if only the instruction set architecture (ISA) or ISA together with some micro architecture features are known. We have successfully applied this methodology to test a RISC processor core
Keywords :
automatic test pattern generation; built-in self test; instruction sets; integrated circuit testing; microprocessor chips; reduced instruction set computing; RISC processors self-test; functional test generation; instruction set architecture; Automatic testing; Built-in self-test; Circuit faults; Circuit testing; Computer architecture; Instruction sets; Microarchitecture; Microprocessors; Reduced instruction set computing; Software testing;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Conference_Location :
Prague
Print_ISBN :
1-4244-0185-2
DOI :
10.1109/DDECS.2006.1649575
