Title :
How to Improve a set of design validation data by using mutation-based test
Author :
Serrestou, Y. ; Beroulle, V. ; Robach, C.
Author_Institution :
LCIS-INPG, Valence
Abstract :
In current hardware design flow, functional verification is widely acknowledged as the crucial step. This paper presents a new contribution to reduce the cost of this step by automating it. We address here, one of the principal challenges of dynamic verification, by providing a new approach for automatic test generation. This approach combines mutation-based test techniques and genetic algorithms to produce stimuli for design under test. The feasibility of the proposed approach is assessed with a preliminary implementation, and some framework has been tested
Keywords :
automatic test pattern generation; design for testability; electronic engineering computing; genetic algorithms; logic testing; automatic test generation; design under test; design validation data set; dynamic verification; functional verification; genetic algorithms; hardware design flow; mutation test techniques; Algorithm design and analysis; Automatic testing; Cost function; Feedback loop; Genetic algorithms; Genetic mutations; Hardware; Qualifications; Software testing; Space exploration;
Conference_Titel :
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Conference_Location :
Prague
Print_ISBN :
1-4244-0185-2
DOI :
10.1109/DDECS.2006.1649576