Title :
Design of a scan line image processor chip
Author :
Chang, Hyunman ; Ong, Soohwan ; Lee, Changhee ; Sunwoo, Myung H.
Author_Institution :
Sch. of Electron. & Comput. Eng., Ajou Univ., Suwon, South Korea
fDate :
31 May-3 Jun 1998
Abstract :
This paper describes a linear array image processor chip called the SliM-II image processor. The chip has 64 processing elements (PEs) connected by a linear array. In contrast to existing array processors, each PE has a multiplier that is quite effective for convolution, template matching, etc. The instruction set can execute an ALU, a data I/O, and an inter-PE communication operations simultaneously in an instruction cycle. In addition, during the ALU/multiplier operation, SliM-II provides parallel data load/store between the register file and on-chip memory as in DSP chips. The SliM-II chip has been implemented, which contains about 1.5 million transistors in a 13.2×13.0 mm2 die size and the package type is 208 pin PQ2. The performance estimation shows a significant improvement compared with existing array processors
Keywords :
CMOS digital integrated circuits; VLSI; convolution; digital signal processing chips; image processing; image processing equipment; parallel architectures; performance evaluation; real-time systems; 0.6 micron; 3.3 V; 30 to 40 MHz; ALU operations; DSP chip; SliM-II; array processor; convolution; data I/O opreations; instruction set; inter-PE communication operations; linear array image processor chip; multiplier; parallel data load/store; performance estimation; scan line image processor chip; template matching; Adders; Convolution; Decoding; Digital signal processing chips; Image processing; Inspection; Packaging; Registers; Streaming media; Surveillance;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706967
