A New 6-bit Flash A/D Converter using Novel Two-Step Structure

Author

Hsia, Shih-Chang ; Lee, Wen-Ching

Author_Institution

Dept. of Comput. & Commun. Eng., Nat. Kaohsiung First Univ. of Sci. & Technol.

fYear

2006

fDate

18-21 April 2006

Firstpage

101

Lastpage

105

Abstract

In this study, we develop a new kind of 6-bit flash ADC with a new two-step structure to greatly reduce the chip size. The first coarse 4-bit uses an array of CMOS inverters rather than comparators for flash conversion. To detect various input signal levels, we adjust the ratio of channel length and width in the CMOS inverters to change the transition threshold. The result of coarse 4-bit is used to generate a reference level for fine 2-bit converting using full parallel structure. The advantages are that the ADC circuit can save reference resistors and reduce power dissipation. The new 6-bit ADC chip dissipates only 13mW using 0.35mum process when it works at 100MHz

Keywords

CMOS integrated circuits; analogue-digital conversion; integrated circuit design; invertors; low-power electronics; 0.35 micron; 100 MHz; 13 mW; 6 bit; ADC circuit; CMOS inverters; chip size reduction; flash AD converter; flash conversion; power dissipation reduction; reference resistor reduction; Analog circuits; Analog-digital conversion; Application software; Capacitors; Complexity theory; Digital circuits; Energy consumption; Inverters; Power dissipation; Split gate flash memory cells;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE

Conference_Location

Prague

Print_ISBN

1-4244-0185-2

Type

conf

DOI

10.1109/DDECS.2006.1649587

Filename

1649587