Design verification of complex microprocessors

As the complexity of microprocessor increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for the compatible microprocessor design. To guarantee the perfect compatibility with previous microprocessors, we developed these C models in different representation levels, i.e Polaris MCV (Micro-Code Verifier) and StreC. An instruction behavioral level C model (Polaris) is verified using the slowed-down PC. In the implementation of micro-architecture, a micro-operational level model (MCV) and RTL model (StreC), both written in C, are co-simulated with consistency checking (IPC) between these two models. The simulation speed of C models makes it possible to test the “real-world” application programs on the C model with a software board model (VPC). To increase the confidence level of verifications, Pro-filer reports the verification coverage of the test program, which is fed back to the automatic test program generator (Pandora). Restartability feature also helps significantly reduce the total simulation time. Using the proposed verification methodology, we designed and verified the K 486, an Intel 486-compatible microprocessor successfully