• DocumentCode
    2187331
  • Title

    Clock distribution networks with on-chip transmission lines

  • Author

    Mizuno, Masayuki ; Anjo, Kenichiro ; Sumi, Yoshikazu ; Fukaishi, Muneo ; Wakabayashi, Hitoshi ; Mogami, Tohru ; Horiuchi, Tadahiko ; Yamashina, Masakazu

  • Author_Institution
    NEC Corp., Kanagawa, Japan
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    3
  • Lastpage
    5
  • Abstract
    Today´s fabrication process scaling enables on-chip lossy transmission lines to be used for long interconnects and high-speed clocking. Advantages and design tradeoffs of on-chip transmission lines are discussed and a 100-mm2 5-GHz clocking chip using on-chip transmission lines is introduced
  • Keywords
    ULSI; clocks; high-speed integrated circuits; integrated circuit design; integrated circuit interconnections; transmission lines; 5 GHz; ULSI design; clock distribution network; high-speed interconnect; on-chip transmission line; Clocks; Degradation; Delay; Fabrication; Inductance; Network-on-a-chip; Power transmission lines; Propagation losses; Transmission lines; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Interconnect Technology Conference, 2000. Proceedings of the IEEE 2000 International
  • Conference_Location
    Burlingame, CA
  • Print_ISBN
    0-7803-6327-2
  • Type

    conf

  • DOI
    10.1109/IITC.2000.854080
  • Filename
    854080
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2187331