• DocumentCode
    2187438
  • Title

    A 0.24 mW, 14.4 kbps, r=1/2, K=9 Viterbi decoder

  • Author

    Kang, Inyup ; Willson, Alan N., Jr.

  • Author_Institution
    Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
  • fYear
    1997
  • fDate
    5-8 May 1997
  • Firstpage
    603
  • Lastpage
    606
  • Abstract
    An r=1/2, K=9 Viterbi decoder IC for CDMA transceivers consumes 0.24 mW at a power supply voltage of 1.65 V, a data rate of 14.4 kbps, and a clock speed of 0.9216 MHz. Its core consists of approximately 65 k transistors, occupying 1.9×3.4 mm2 in a 0.8-μm triple-layer-metal n-well CMOS technology
  • Keywords
    CMOS digital integrated circuits; VLSI; Viterbi decoding; cellular radio; code division multiple access; digital radio; digital signal processing chips; telecommunication computing; transceivers; 0.24 W; 0.8 micron; 0.9216 MHz; 1.65 V; 14.4 kbit/s; CDMA transceivers; Viterbi decoder IC; n-well CMOS technology; triple-layer-metal technology; Clocks; Decoding; Delay; Memory management; Phasor measurement units; Power dissipation; Reflective binary codes; Shift registers; Throughput; Viterbi algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference, 1997., Proceedings of the IEEE 1997
  • Conference_Location
    Santa Clara, CA
  • Print_ISBN
    0-7803-3669-0
  • Type

    conf

  • DOI
    10.1109/CICC.1997.606698
  • Filename
    606698
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2187438