A Switch Supporting Circuit and Packet Switching for On-Chip Networks

Author

Hsin-Chou Chi ; Chia-Ming Wu ; Sung-Tze Wu

Author_Institution

Dept. of Comput. Sci. & Inf. Eng., National Dong Hwa Univ., Hualien

fYear

2006

fDate

18-21 April 2006

Firstpage

224

Lastpage

225

Abstract

In this paper, the design of a hybrid switch for on-chip networks in SoC design is presented. This hybrid switch provides both guaranteed and best-effort communication services for network-on-chip architectures. We use the pre-scheduled circuit-switched network to support guaranteed communication service between IPs on the chip. In order to fully utilize the network bandwidth, we further incorporate the packet-switched architecture. Our design has been experimentally implemented using UMC 0.18 mum technology. It has an aggregate bandwidth of 5 times 434MHz times 64 bits = 139 Gb/s. Compared to previous designs, our switch provides high performance with a reasonable cost

Keywords

integrated circuit design; nanotechnology; network-on-chip; packet switching; 0.18 micron; 139 Gbit/s; communication services; hybrid switch design; integrated circuit design; nanotechnology; network-on-chip architectures; on-chip networks; packet switching; pre-scheduled circuit-switched network; switch supporting circuit; system on chip; Bandwidth; Circuit topology; Communication switching; Costs; Network topology; Network-on-a-chip; Packet switching; Routing; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE

Conference_Location

Prague

Print_ISBN

1-4244-0185-2

Type

conf

DOI

10.1109/DDECS.2006.1649619

Filename

1649619