DocumentCode
2187633
Title
Detection, Localisation and Identification of Interconnection Faults Using MISR Compactor
Author
Garbolino, T. ; Kopec, M. ; Gucwa, K. ; Hlawiczka, A.
Author_Institution
Silesian Univ. of Technol., Gliwice
fYear
2006
fDate
18-21 April 2006
Firstpage
228
Lastpage
229
Abstract
The paper introduces a novel idea of interconnect fault detection, localization and identification based on test response compaction using a MISR. The above-mentioned operations are made at-speed. The localization is done by means of three long, full diagnostic resolution sequences: Walking 1 (W1), Walking 0 (W0) and a part of Johnson sequence (J). The final fault identification phase exploits information stored in two or three signatures
Keywords
fault simulation; integrated circuit testing; logic testing; Johnson sequence; MISR compactor; Walking 1; fault detection; fault identification; fault localisation; full diagnostic resolution sequences; integrated circuit interconnection; test response compaction; walking 0; Circuit faults; Compaction; Electrical fault detection; Fault detection; Fault diagnosis; Frequency; Integrated circuit interconnections; Legged locomotion; Multiprocessor interconnection networks; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design and Diagnostics of Electronic Circuits and systems, 2006 IEEE
Conference_Location
Prague
Print_ISBN
1-4244-0185-2
Type
conf
DOI
10.1109/DDECS.2006.1649621
Filename
1649621
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