Title :
A CPLD design of a self-organizing system for data clustering
Author :
Ohkubo, Jun Ya ; Miyanaga, Yoshikazu ; Tochinai, Koji
Author_Institution :
Graduate Sch. of Eng., Hokkaido Univ., Sapporo, Japan
fDate :
31 May-3 Jun 1998
Abstract :
A hardware design of a self-organizing system is presented in this report. A high performance parallel processor is designed with pipeline modules. The size of this system is programmable within a certain degree. In this paper, we design this system using a target CPLD. In addition, this paper shows the error analysis of floating-point operation to estimate the optimum word length of data for the minimization of circuit resources
Keywords :
VLSI; data handling; error analysis; floating point arithmetic; logic CAD; microprocessor chips; parallel architectures; pipeline processing; programmable logic devices; self-adjusting systems; CPLD design; complex PLD; data clustering; error analysis; floating-point operation; hardware design; high performance parallel processor; optimum word length estimation; pipeline modules; self-organizing system; Circuits; Clustering algorithms; Clustering methods; Costs; Data engineering; Design engineering; Euclidean distance; Field programmable gate arrays; Hardware; Programmable logic arrays;
Conference_Titel :
Circuits and Systems, 1998. ISCAS '98. Proceedings of the 1998 IEEE International Symposium on
Conference_Location :
Monterey, CA
Print_ISBN :
0-7803-4455-3
DOI :
10.1109/ISCAS.1998.706971
